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Synchronous Buck Pseudo-Fixed Frequency Power Supply Controller
POWER MANAGEMENT Description
The SC411 is a constant on-time synchronous buck PWM controller in a space-saving MLPQ package intended for use in notebook computers and other battery operated portable devices. Features include high efficiency and a fast dynamic response with no minimum on-time. The excellent transient response means that SC411 based solutions will require less output capacitance than competing fixed frequency converters. The switching frequency is constant until a step-in load or line voltage occurs. During this time the pulse density and frequency will increase or decrease to counter the change in output or input voltage. After the transient event, the controller frequency will return to steady-state operation. At light loads, Powersave Mode enables the SC411 to skip PWM pulses for better efficiency. The output voltage can be adjusted from 0.5V to VCCA. A frequency setting resistor sets the on-time for the controller. The integrated gate drivers feature adaptive shoot-through protection and soft-switching. Additional features include cycle-by-cycle current limit, digital soft-start, over-voltage and under-voltage protection, a Power Good output and soft discharge upon shutdown.
SC411
Features
Constant on-time for fast dynamic response Programmable VOUT range = 0.5 - VCCA VBAT range = 1.8V - 25V DC current sense using low-side RDS(ON) Sensing or sense resistor Resistor programmable frequency Cycle-by-cycle current limit Digital soft-start Powersave option Over-voltage/under-voltage fault protection 10A typical shutdown current Low quiescent power dissipation Power good indicator 1.2% reference Integrated gate drivers with soft switching Enable pin 16 pin MLPQ (4mm x 4mm) Output soft discharge upon shutdown
Applications
Notebook Computers CPU/IO Supplies Handheld Terminals and PDAs LCD Monitors Network Power Supplies
Typical Application Circuit
VBAT 5VSUS 5VSUS VBAT
R1 RTON1 D1 C1 0.1uF R2
15
14
10R
U1
16
EN/PSV
TON
BST
NC
13
Q1 DH LX 12 11 10 9 R5
C2 10uF
VOUT C3 R4 R3
1 2 3 4
VOUT VCCA
L1 VOUT C4 + Q2
SC411
FB PGD ILIM VDDP
PGOOD R6
C5 1nF
C6
PGND 7
VSSA
TPAD
NC
1uF
5
6
8
DL
C7 1uF
June 2007
1
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SC411
POWER MANAGEMENT Absolute Maximum Ratings(1)
Exceeding the specifications below may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability.
Parameter TON to VSSA DH, BST to PGND LX to PGND PGND to VSSA BST to LX DL, ILIM, VDDP to PGND EN/PSV, FB, PGD, VCCA, VOUT to VSSA VCCA to EN/PSV, FB, PGD, VOUT Thermal Resistance Junction to Ambient((2)
2)
Symbol
Maximum -0.3 to +25.0 -0.3 to +30.0 -2.0 to +25.0 -0.3 to +0.3 -0.3 to +6.0
-
Units V V V V V V V V C/W C C C
0.3 to +6.0
-0.3 to +6.0 -0.3 to +6.0 JA TJ TSTG TPKG 31 -40 to +125 -65 to +150 260
Operating Junction Temperature Range Storage Temperature Range IR Reflow (Soldering) 10s to 30s
Notes: 1) This device is ESD sensitive. Use of standard ESD handling precautions is required. 2) Calculated from package in still air, mounted to 3" to 4.5", 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
Electrical Characteristics
Test Conditions: VBAT = 15V, EN/PSV = 5V, VCCA = VDDP = 5V, VOUT =1.25V, RTON = 1M.
25C Parameter Conditions Min Input Supplies VCCA VDDP VBAT Voltage VDDP Operating Current VCCA Operating Current Off-time > 800ns FB > regulation point, ILOAD = 0A FB > regulation point, ILOAD = 0A
2
-40C to 125C Units Max Min Max
Typ
5.0 5.0 1.8 70 700 25
4.5 4.5
5.5 5.5
V V V
150 1100
A A
(c) 2007 Semtech Corp.
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SC411
POWER MANAGEMENT Electrical Characteristics (Cont.)
25C Parameter Conditions Min Input Supplies (Cont.) TON Operating Current RTON = 1M EN/PSV = 0V Shutdown Current VCCA VDDP, TON Controller Error Comparator Threshold (FB Turn-on Threshold)(1) Output Voltage Range On-Time, VBAT = 2.5V Minimum Off-Time VOUT Input Resistance VOUT Shutdown Discharge Resistance FB Input Bias Current Over-Current Sensing ILIM Source Current Current Comparator Offset PSAVE Zero-Crossing Threshold Fault Protection (PGND - LX), EN/PSV = 5V 5 mV DL high PGND - ILIM 10 9 -10 11 10 A mV EN/PSV = GND RTON = 1M RTON = 500k 1761 936 400 500 22 -1.0 +1.0 VCCA = 4.5V to 5.5V Includes variations of internal x3 gain stage, comparator, and 1.5V REF 15 -5 5 0 -10 10 1 A A A A Typ Max Min Max -40C to 125C Units
0.500
-1.2%
+1.2%
V V
ns
0.5 1409 749
VCCA 2113 1123 550
ns k
A
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SC411
POWER MANAGEMENT Electrical Characteristics (Cont.)
25C Parameter Conditions Min (PGND - LX), RILIM = 5k Current Limit (Positive)
(2)
-40C to 125C Units Max Min 35 80 170 Max 65 120 230 mV mV mV
Typ 50 100 200
(PGND - LX), RILIM = 10k (PGND - LX), RILIM = 20k
Fault Protection (Cont.) Current Limit (Negative) Output Under-Voltage Fault Output Over-Voltage Fault Over-Voltage Fault Delay PGD Low Output Voltage PGD Leakage Current PGD UV Threshold PGD Fault Delay VCCA Under-Voltage Threshold Over-Temperature Lockout Inputs/Outputs Logic Input Low Voltage Logic Input High Voltage Logic Input High Voltage EN/PSV Input Resistance R Pulldown to VSSA 1.0 EN/PSV Low EN High, PSV Low (Floating) EN/PSV High R Pullup to VCCA 1.5 M 2.0 3.1 1.2 V V V (PGND - LX) With respect to internal ref. With respect to internal ref. FB forced above OV Threshold Sink 1mA FB in regulation, PGD = 5V With respect to internal ref. FB forced outside PGD window Falling (100mV Hysteresis) 10C Hysteresis -10 5 4.0 165 3.7 4.3 -12 -125 -30 +16 5 0.4 1 -8 -160 -40 +12 -90 -25 +20 mV % % s V A % s V C
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SC411
POWER MANAGEMENT Electrical Characteristics (Cont.)
25C Parameter Conditions Min Soft-Start Soft-Start Ramp Time Under-Voltage Blank Time Gate Drivers Shoot-Through Delay(4) DL Pull-Down Resistance DL Sink Current DL Pull-Up Resistance DL Source Current DH or DL Rising DL Low DL = 2.5V DL High DL = 2.5V 30 0.80 3.1 2 1.3 4 1.75 ns A A EN/PSV High to PGD High EN/PSV High to UV High 440 440 clks(3) clks(3) Typ Max Min Max -40C to 125C Units
Notes: 1) When the inductor is in continuous and discontinuous conduction mode, the output voltage will have a DC regulation level higher than the error-comparator threshold by 50% of the ripple voltage. 2) Using a current sense resistor, this measurement relates to PGND minus the voltage of the source on the low-side MOSFET. These values guaranteed by the ILIM Source Current and Current Comparator Offset tests. 3) clks = Switching cycles. 4) Guaranteed by design. See Shoot-Through Delay Timing Diagram on Page 8. 5) Semtech's SmartDriverTM FET drive first pulls DH high with a pull-up resistance of 10 (typ) until LX = 1.5V (typ). At this point, an additional pull-up device is activated, reducing the resistance to 2 (typ). This negates the need for an external gate or boost resistor.
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SC411
POWER MANAGEMENT Block Diagram
VCCA (2) EN/PSV (15) DSCHG
POR / SS
OT
BST (13) TON (16) VOUT (1) TON ON OFF PWM DSCHG TOFF CONTROL LOGIC HI DH (12) LX (11)
OC 1.5V REF + VDDP (9) FB (3) X3 LO DL (8) PGND (7) OV VSSA (6) FAULT MONITOR UV REF + 16% REF - 10% REF - 30% NC (5) NC (14) ZERO ISENSE ILIM (10)
Error Comparator
PGD (4)
Note: the Error Comparator tolerances are approximately x3 gain stage = +/- 0.1% gain error comparator = +/- 3mV offset error 1.5V REF = +/- 1.0%
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SC411
POWER MANAGEMENT Pin Configuration
EN/PSV TON BST
Ordering Information
Device
NC
Package(1) MLPQ-16 Evaluation Board
SC411MLTRT(2) SC411EVB
12 11 10
16
15
14
13
VOUT VCCA FB PGD
1 2 3 4 5
TOP VIEW
DH LX ILIM VDDP
T 6 7 8
Notes: 1) Only available in tape and reel packaging. A reel contains 3000 devices. (2) Lead free product. This product is fully WEEE, RoHS and J-STD-020B compliant.
9
PGND
VSSA
NC
MLPQ16: 4X4 BODY
Pin Descriptions
Pin # 1 2 3 4 5 6 7 8 9 10 11 Pin Name VOUT VCCA FB PGD NC VSSA PGND DL VDDP ILIM LX Pin Function Output voltage sense input. Connect to the output at the load. Supply voltage input for the analog supply. Use a 10 /1F RC filter from 5VSUS to VSSA. Feedback input. Connect to a resistor divider located at the IC from VOUT to VSSA to set the output voltage from 0.5V to VCCA. Power Good open drain NMOS output. Goes high after a fixed clock cycle delay (440 cycles) following power up. Not Connected. Ground reference for analog circuitry. Connect directly to thermal pad. Power ground. Connect directly to thermal pad. Gate drive output for the low side MOSFET switch. +5V supply voltage input for the gate drivers. Decouple this pin with a 1F ceramic capacitor to PGND. Current limit input. Connect to drain of low-side MOSFET for RDS(on) sensing or the source for resistor sensing through a threshold sensing resistor. Phase node (junction of top and bottom MOSFETs and the output inductor) connection.
(c) 2007 Semtech Corp.
DL
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SC411
POWER MANAGEMENT Pin Descriptions (Cont.)
12 13 14 DH BST NC Gate drive output for the high side MOSFET switch. Boost capacitor connection for the high side gate drive. Not connected. Enable/Power Save input. Pull down to VSSA to shut down VOUT and discharge it through 22 (nom.). Pull up to enable VOUT and activate PSAVE mode. Float to enable VOUT activate continuous conduction mode (CCM). If floated, bypass to VSSA with a 10nF ceramic capacitor. This pin is used to sense VBAT through a pullup resistor, RTON, and to set the top MOSFET on-time. Bypass this pin with a 1nF ceramic capacitor to VSSA. Pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected internally.
15
EN/PSV
16 -
TON Thermal Pad
Shoot-Through Delay Timing Diagram
LX
DH
DL DL tplhDL tplhDH
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SC411
POWER MANAGEMENT Application Information
+5V Bias Supplies The SC411 requires an external +5V bias supply in addition to the battery. If stand-alone capability is required, the +5V supply can be generated with an external linear regulator such as the Semtech LP2951. For optimal operation, the controller has its own ground reference, VSSA, which should be tied along with PGND directly to the thermal pad under the part, which in turn should connect to the ground plane using multiple vias. All external components referenced to VSSA in the Typical Application Circuit on Page 1 located near their respective pins. Supply decoupling capacitors should be located adjacent to their respective pins. A 10 resistor should be used to decouple VCCA from the main VDDP supply. All ground connections are connected directly to the ground plane as mentioned above. VSSA and PGND should be starred at the thermal pad. The VDDP input provides power to the upper and lower gate drivers; a decoupling capacitor is required. No series resistor between VDDP and 5V is required. See Layout Guidelines on page 17 for more details. Pseudo-Fixed Frequency Constant On-Time PWM Controller The PWM control architecture consists of a constant ontime, pseudo fixed frequency PWM controller (Block Diagram, Page 6). The output ripple voltage developed across the output filter capacitor's ESR provides the PWM ramp signal eliminating the need for a current sense resistor. The high-side switch on-time is determined by a one-shot whose period is directly proportional to output voltage and inversely proportional to input voltage. A second one-shot sets the minimum off-time which is typically 400ns. On-Time One-Shot (tON) The on-time one-shot comparator has two inputs. One input looks at the output voltage, while the other input samples the input voltage and converts it to a current. This input voltage-proportional current is used to charge an internal on-time capacitor. The on-time is the time required for the voltage on this capacitor to charge from zero volts to VOUT, thereby making the on-time of the high-side switch directly proportional to output voltage and inversely proportional to input voltage. This implementation results
(c) 2007 Semtech Corp. 9
in a nearly constant switching frequency without the need for a clock generator. For VOUT < 3.3V:
V t ON = 3.3 x10 -12 * (R T ON + 37 x10 3 ) * OUT + 50ns V BAT
For 3.3V VOUT 5V:
V t ON = 0.85 * 3.3 x10 -12 * (R T ON + 37 x10 3 ) * OUT + 50ns V BAT
RTON is a resistor connected from the input supply (VBAT) to the TON pin. Due to the high impedance of this resistor, the TON pin should always be bypassed to VSSA using a 1nF ceramic capacitor. EN/PSV: Enable, PSAVE and Soft Discharge The EN/PSV pin enables the supply. When EN/PSV is tied to VCCA the controller is enabled and power save will also be enabled. When the EN/PSV pin is tri-stated, an internal pull-up will activate the controller and power save will be disabled. If PSAVE is enabled, the SC411 PSAVE comparator will look for the inductor current to cross zero on eight consecutive switching cycles by comparing the phase node (LX) to PGND. Once observed, the controller will enter power save and turn off the low side MOSFET when the current crosses zero. To improve light-load efficiency and add hysteresis, the on-time is increased by 50% in power save. The efficiency improvement at lightloads more than offsets the disadvantage of slightly higher output ripple. If the inductor current does not cross zero on any switching cycle, the controller will immediately exit power save. Since the controller counts zero crossings, the converter can sink current as long as the current does not cross zero on eight consecutive cycles. This allows the output voltage to recover quickly in response to negative load steps even when PSAVE is enabled. If the EN/PSV pin is pulled low, the related output will be shut down and discharged using a switch with a nominal resistance of 22 Ohms. This will ensure that the output is in a defined state next time it is enabled and also ensure, since this is a soft discharge, that there are no dangerous negative voltage excursions to be concerned about. In order for the soft discharge circuitry to function correctly, the chip supply must be present.
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SC411
POWER MANAGEMENT Application Information (Cont.)
Output Voltage Selection The output voltage is set by the feedback resistors R3 & R5 of Figure 2 below. The internal reference is 1.5V, so the voltage at the feedback pin is multiplied by three to match the 1.5V reference. Therefore the output can be set to a minimum of 0.5V. The equation for setting the output voltage is:
R3 VOUT = ( 1 + ) * 0.5 R5
tor. In an extreme over-current situation, the top MOSFET will never turn back on and eventually the part will latch off due to output under-voltage (see Output Under-voltage Protection). The current sensing circuit actually regulates the inductor valley current (see Figure 3). This means that if the current limit is set to 10A, the peak current through the inductor would be 10A plus the peak ripple current, and the average current through the inductor would be 10A plus 1/2 the peak-to-peak ripple current. The equations for setting the valley current and calculating the average current through the inductor are shown below:
16
14
U1
15
TON
VOUT C5 56p 0402 R3 20k0 0402
EN/PSV
BST
NC
13
1
VOUT
DH
12
2
VCCA
LX
11
3
SC411
FB ILIM
10
4
PGD
VDDP
9
NC
5
6
Figure 2: Setting The Output Voltage Current Limit Circuit Current limiting of the SC411 can be accomplished in two ways. The on-state resistance of the low-side MOSFET can be used as the current sensing element or sense resistors in series with the low-side source can be used if greater accuracy is desired. RDS(ON) sensing is more efficient and less expensive. In both cases, the RILIM resistor between the ILIM pin and LX pin sets the over current threshold. This resistor RILIM is connected to a 10A current source within the SC411 which is turned on when the low side MOSFET turns on. When the voltage drop across the sense resistor or low side MOSFET equals the voltage across the RILIM resistor, positive current limit will activate. The high side MOSFET will not be turned on until the voltage drop across the sense element (resistor or MOSFET) falls below the voltage across the RILIM resis-
7
8
DL
R5 14k3 0402
VSSA
TPAD
PGND
Figure 3: Valley Current Limiting The equation for the current limit threshold is as follows: ILIMIT = 10A x RILIM / RSENSE (Amps) Where (referring to Figure 4 on Page 17) RILIM is R4 and RSENSE is the RDS(ON) of Q2. For resistor sensing, a sense resistor is placed between the source of Q2 and PGND. The current through the source sense resistor develops a voltage that opposes the voltage developed across RILIM. When the voltage developed across the RSENSE resistor reaches the voltage drop across RILIM, a positive over-current exists and the high side MOSFET will not be allowed to turn on. When using an external sense resistor RSENSE is the resistance of the sense resistor.
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SC411
POWER MANAGEMENT Application Information (Cont.)
The current limit circuitry also protects against negative over-current (i.e. when the current is flowing from the load to PGND through the inductor and bottom MOSFET). In this case, when the bottom MOSFET is turned on, the phase node, LX, will be higher than PGND initially. The SC411 monitors the voltage at LX, and if it is greater than a set threshold voltage of 125mV (nom) the bottom MOSFET is turned off. The device then waits for approximately 2.5s and then DL goes high for 300ns (typ) once more to sense the current. This repeats until either the overcurrent condition goes away or the part latches off due to output over-voltage (see Output Over-voltage Protection). Power Good Output The power good output is an open-drain output and requires a pull-up resistor. When the output voltage is 16% above or 10% below its set voltage, PGD gets pulled low. It is held low until the output voltage returns to within these tolerances once more. PGD is also held low during startup and will not be allowed to transition high until soft start is over (440 switching cycles) and the output reaches 90% of its set voltage. There is a 5s delay built into the PGD circuitry to prevent false transitions. Output Over-Voltage Protection When the output exceeds 16% of the its set voltage the low-side MOSFET is latched on. It stays latched on and the controller is latched off until reset*. There is a 5s delay built into the OV protection circuit to prevent false transitions. Output Under-Voltage Protection When the output is 30% below its set voltage the output is latched in a tri-stated condition. It stays latched and the controller is latched off until reset*. There is a 5s delay built into the UV protection circuit to prevent false transitions. POR, UVLO and Soft-Start An internal power-on reset (POR) occurs when VCCA exceeds 3V, starting up the internal biasing. VCCA undervoltage lockout (UVLO) circuitry inhibits the controller until VCCA rises above 4.2V. At this time the UVLO circuitry
* Note: to reset from any fault, VCCA or EN/PSV must be toggled. (c) 2007 Semtech Corp. 11 www.semtech.com
resets the fault latch and soft-start counter, and allows switching to occur if the device is enabled. Switching always starts with DL to charge up the BST capacitor. With the soft-start circuit (automatically) enabled, it will progressively limit the output current (by limiting the current out of the ILIM pin) over a predetermined time period of 440 switching cycles. The ramp occurs in four steps: 1) 110 cycles at 25% ILIM with double minimum off-time (for purposes of the on-time one-shot, there is an internal positive offset of 120mV to VOUT during this period to aid in startup). 2) 110 cycles at 50% ILIM with normal minimum offtime. 3) 110 cycles at 75% ILIM with normal minimum off-time. 4) 110 cycles at 100% ILIM with normal minimum offtime. At this point the output under-voltage and power good circuitry is enabled. There is 100mV of hysteresis built into the UVLO circuit and when VCCA falls to 4.1V (nom) the output drivers are shut down and tri-stated. MOSFET Gate Drivers The DH and DL drivers are optimized for driving moderate-sized high-side, and larger low-side power MOSFETs. An adaptive dead-time circuit monitors the DL output and prevents the high-side MOSFET from turning on until DL is fully off (below ~1V). Semtech's SmartDriverTM FET drive first pulls DH high with a pull-up resistance of 10 (typ) until LX = 1.5V (typ). At this point, an additional pull-up device is activated, reducing the resistance to 2 (typ); This negates the need for an external gate or boost resistor. The adaptive dead time circuit also monitors the phase node, LX, to determine the state of the high side MOSFET, and prevents the low side MOSFET from turning on until DH is fully off (LX below ~1V). Be sure there is low resistance and low inductance between the DH and DL outputs to the gate of each MOSFET.
SC411
POWER MANAGEMENT Application Information (Cont.)
Dropout Performance The output voltage adjust range for continuous-conduction operation is limited by the fixed 550ns (maximum) minimum off-time one-shot. For best dropout performance, use the slowest on-time setting of 200kHz. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. The IC duty-factor limitation is given by:
DUTY =
t ON ( MIN ) t ON ( MIN )
Switching frequency variation with load can be minimized by choosing MOSFETs with lower RDS(ON). High RDS(ON) MOSFETs will cause the switching frequency to increase as the load current increases. This will reduce the ripple and thus the DC output voltage. Design Procedure Prior to designing an output and making component selections, it is necessary to determine the input voltage range and the output voltage specifications. For purposes of demonstrating the procedure the output for the schematic in Figure 4 on Page 17 will be designed. The maximum input voltage (VBAT(MAX)) is determined by the highest AC adaptor voltage. The minimum input voltage (VBAT(MIN)) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches. For the purposes of this design example we will use a VBAT range of 8V to 20V. Four parameters are needed for the output: 1) nominal output voltage, VOUT (we will use 1.2V). 2) static (or DC) tolerance, TOLST (we will use +/-4%). 3) transient tolerance, TOLTR and size of transient (we will use +/-8% and 6A for purposes of this demonstration). 4) maximum output current, IOUT (we will design for 6A). Switching frequency determines the trade-off between size and efficiency. Increased frequency increases the switching losses in the MOSFETs, since losses are a function of VIN2. Knowing the maximum input voltage and budget for MOSFET switches usually dictates where the design ends up. A default RtON value of 1M is suggested as a starting point, but this is not set in stone. The first thing to do is to calculate the on-time, tON, at VBAT(MIN) and VBAT(MAX), since this depends only upon VBAT, VOUT and RtON. For VOUT < 3.3V:
tON_VBAT(MIN) = 3.3 10-12 RtON + 37 103 VOUT + 50 10-9 s VBAT(MIN)
+ t OFF (MAX )
Be sure to include inductor resistance and MOSFET onstate voltage drops when performing worst-case dropout duty-factor calculations. SC411 System DC Accuracy Two IC parameters affect system DC accuracy, the error comparator threshold voltage variation and the switching frequency variation with line and load. The error comparator threshold does not drift significantly with supply and temperature. Thus, the error comparator contributes 1.2% or less to DC system inaccuracy. Board components and layout also influence DC accuracy. The use of 1% feedback resistors contribute 1%. If tighter DC accuracy is required use 0.1% feedback resistors. The on-pulse in the SC411 is calculated to give a pseudo- fixed frequency. Nevertheless, some frequency variation with line and load can be expected. This variation changes the output ripple voltage. Because constant-on regulators regulate to the valley of the output ripple, 1/2 of the output ripple appears as a DC regulation error. For example, if the feedback resistors are chosen to divide down the output by a factor of five, the valley of the output ripple will be VOUT. For example: if VOUT is 2.5V and the ripple is 50mV with VBAT = 6V, then the measured DC output will be 2.525V. If the ripple increases to 80mV with VBAT = 25V, then the measured DC output will be 2.540V. The output inductor value may change with current. This will change the output ripple and thus the DC output voltage but it will not change the frequency.
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SC411
POWER MANAGEMENT Application Information (Cont.)
and,
-12 tON_VBAT(MAX) = 3.3 10
and,
RtON + 37 103 VOUT VBAT(MAX) + 50 10-9 s
IRIPPLE_VBAT(MAX) = VBAT(MAX)
VOUT
tON_VBAT(MAX) L
AP-P
From these values of tON we can calculate the nominal switching frequency as follows:
fSW _ VBAT(MIN ) = VOUT Hz (VBAT(MIN ) * t ON _ VBAT(MIN ) )
For our example: IRIPPLE_VBAT(MIN) = 1.74AP-P and IRIPPLE_VBAT(MAX) = 2.18AP-P From this we can calculate the minimum inductor current rating for normal operation:
IINDUCT OR(MIN ) = IOUT (MAX ) + IRIPPLE_ VBAT(MAX ) 2 A (MIN )
and,
fSW _ VBAT(MAX ) =
VOUT Hz (VBAT(MAX ) * t ON _ VBAT(MAX ) )
For our example: tON is generated by a one-shot comparator that samples VBAT via RtON, converting this to a current. This current is used to charge an internal 3.3pF capacitor to VOUT. The equations above reflect this along with any internal components or delays that influence tON. For our example we select RtON = 1M: tON_VBAT(MIN) = 563ns and tON_VBAT(MAX) = 255ns
fSW_VBAT(MIN)
IINDUCTOR(MIN) = 7.1A(MIN) Next we will calculate the maximum output capacitor equivalent series resistance (ESR). This is determined by calculating the remaining static and transient tolerance allowances. Then the maximum ESR is the smaller of the calculated static ESR (RESR_ST(MAX)) and transient ESR (RESR_TR(MAX)):
RESR_ ST(MAX ) =
= 266kHz and fSW_VBAT(MAX) = 235kHz
(ERR
Now that we know tON we can calculate suitable values for the inductor. To do this we select an acceptable inductor ripple current. The calculations below assume 50% of IOUT which will give us a starting place.
ST - ERR DC )* 2 Ohms IRIPPLE_ VBAT(MAX )
LVBAT(MIN) = VBAT(MIN)
VOUT
tON_VBAT(MIN) 0.5 IOUT
H
Where ERRST is the static output tolerance and ERRDC is the DC error. The DC error will be 1.2% plus the tolerance of the feedback resistors, thus 2.2% total for 1% feedback resistors. For our example:
and,
LVBAT(MAX) = VBAT(MAX)
For our example:
VOUT
tON_VBAT(MAX) 0.5 IOUT
H
ERRST = 48mV and ERRDC = 26.4mV, therefore, RESR_ST(MAX) = 19.8m
RESR_ T R(MAX ) =
(ERR
TR
- ERR DC )
LVBAT(MIN) = 1.3H and LVBAT(MAX) = 1.6H We will select an inductor value of 2.2H to reduce the ripple current, which can be calculated as follows:
IRIPPLE_VBAT(MIN) = VBAT(MIN) VOUT tON_VBAT(MIN) L AP-P
I IOUT + RIPPLE_ VBAT(MAX ) 2
Ohms
Where ERRTR is the transient output tolerance. Note that this calculation assumes that the worst case load transient is full load. For half of full load, divide the IOUT term by 2.
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SC411
POWER MANAGEMENT Application Information (Cont.)
For our example: ERRTR = 96mV and ERRDC = 26.4mV, therefore, RESR_TR(MAX) = 9.8m for a full 6A load transient We will select a value of 12.5m maximum for our design, which would be achieved by using two 25m output capacitors in parallel. Note that for constant-on converters there is a minimum ESR requirement for stability which can be calculated as follows:
RESR(MIN ) 3 = 2 * * COUT * fSW
Firstly calculating the value of ZTOP required:
Z T OP = RBOT * ( RIPPLE_ VBAT(MIN ) - 0.015 )Ohms V 0.015
Secondly calculating the value of CTOP required to achieve this:
C T OP 1 1 - Z R T OP T OP F = 2 * * fSW _ VBAT(MIN )
For our example we will use RTOP = 20.0k and RBOT = 14.3k, therefore, ZTOP = 6.67k and CTOP = 60pF We will select a value of CTOP = 56pF. Calculating the value of VFB based upon the selected CTOP:
RBOT = VRIPPLE_ VBAT(MIN ) * 1 RBOT + 1 + 2 * * fSW _ VBAT(MIN ) * C T OP R T OP VP -P
This criteria should be checked once the output capacitance has been determined. Now that we know the output ESR we can calculate the output ripple voltage:
VRIPPLE_ VBAT(MAX ) = RESR * IRIPPLE_ VBAT(MAX ) VP -P
VFB _ VBAT(MIN )
and,
VRIPPLE_ VBAT(MIN ) = RESR * IRIPPLE_ VBAT(MIN ) VP -P
For our example: VFB_VBAT(MIN) = 14.8mVP-P - good Next we need to calculate the minimum output capacitance required to ensure that the output voltage does not exceed the transient maximum limit, POSLIMTR, starting from the actual static maximum, VOUT_ST_POS, when a load release occurs:
VOUT _ ST _ POS = VOUT + ERR DC V
For our example: VRIPPLE_VBAT(MAX) = 27mVP-P and VRIPPLE_VBAT(MIN) = 22mVP-P Note that in order for the device to regulate in a controlled manner, the ripple content at the feedback pin, VFB, should be approximately 15mVP-P at minimum VBAT, and worst case no smaller than 10mVP-P. If VRIPPLE_VBAT(MIN) is less than 15mVP-P the above component values should be revisited in order to improve this. Quite often a small capacitor, CTOP, is required in parallel with the top feedback resistor, RTOP, in order to ensure that VFB is large enough. CTOP should not be greater than 100pF. The value of CTOP can be calculated as follows, where RBOT is the bottom feedback resistor.
For our example: VOUT_ST_POS = 1.226V
POSLIM T R = VOUT * TOL T R V
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SC411
POWER MANAGEMENT Application Information (Cont.)
Where TOLTR is the transient tolerance. For our example: POSLIMTR = 1.296V The minimum output capacitance is calculated as follows: Finally, we calculate the current limit resistor value. As described in the current limit section, the current limit looks at the "valley current", which is the average output current minus half the ripple current. We use the maximum room temperature specification for MOSFET RDS(ON) at VGS = 4.5V for purposes of this calculation:
IVALLEY = IOUT - IRIPPLE_ VBAT(MIN ) 2 A
CCOUT(MIN) = L
IRIPPLE_VBAT(MAX) 2 IOUT + 2 POSLIMTR2 VOUT_ST_POS2
F
The ripple at low battery voltage is used because we want to make sure that current limit does not occur under normal operating conditions.
RILIM = ( VALLEY * 1.2)* I RDS( ON ) * 1.4 10 * 10 - 6 Ohms
This calculation assumes the absolute worst case condition of a full-load to no load step transient occurring when the inductor current is at its highest. The capacitance required for smaller transient steps may be calculated by substituting the desired current for the IOUT term. For our example: COUT(MIN) = 626F. We will select 440F, using two 220F, 25m capacitors in parallel. For smaller load release overshoot, 660F may be used. Alternatively, one 15m or 12m, 220F, 330F or 470F capacitor may be used (with the appropriate change to the calculation for CTOP), depending upon the load transient requirements. Next we calculate the RMS input ripple current, which is largest at the minimum battery voltage:
IIN(RMS ) = VOUT * ( BAT(MIN ) - VOUT )* V IOUT A RMS VBAT_ MIN
For our example: IVALLEY = 5.13A, RDS(ON) = 9m and RILIM = 7.76k We select the next lowest 1% resistor value: 7.68k Thermal Considerations The junction temperature of the device may be calculated as follows:
TJ = TA + PD * JA C
Where: TA = ambient temperature (C) PD = power dissipation in (W) JA = thermal impedance junction to ambient from absolute maximum ratings (C/W) The power dissipation may be calculated as follows:
For our example: IIN(RMS) = 2.14ARMS Input capacitors should be selected with sufficient ripple current rating for this RMS current, for example a 10F, 1210 size, 25V ceramic capacitor can handle approximately 3ARMS. Refer to manufacturer's data sheets and derate appropriately. Where:
PD = VCCA * IVCCA + VDDP * IVDDP + Vg * Q g * f + VBST * 1mA * D W
VCCA = chip supply voltage (V) IVCCA = operating current (A) VDDP = gate drive supply voltage (V)
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SC411
POWER MANAGEMENT Application Information (Cont.)
IVDDP = gate drive operating current (A) Vg = gate drive voltage, typically 5V (V) Qg = FET gate charge, from the FET datasheet (C) f = switching frequency (kHz) VBST = boost pin voltage during tON (V) D = duty cycle Inserting the following values for VBAT(MIN) condition (since this is the worst case condition for power dissipation in the controller) as an example (VOUT = 1.2V), TA = 85C JA = 100C/W VCCA = VDDP = 5V IVCCA = 1100A (data sheet maximum) IVDDP = 150A (data sheet maximum) Vg = 5V Qg = 60nC f = 266kHz VBAT(MIN) = 8V VBST(MIN) = VBAT(MIN)+VDDP = 13V D(MIN) = 1.2/8 = 0.15 gives us,
PD = 5 * 1100 * 10 -6 + 5 * 150 * 10 -6 + 5 * 60 * 10 -9 * 266 * 10 3 + 13 * 1 * 10 -3 * 0.15 = 0.088 W
and,
TJ = 85 + 0.088 * 100 = 93.8 C
As can be seen, the heating effects due to internal power dissipation are practically negligible, thus requiring no special thermal consideration during layout. The Reference Design is shown in Figure on Page 17. An additional design optimized for efficiency and capable of a higher load current of 10A is shown in Figure 11 on Page 21.
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SC411
POWER MANAGEMENT
Layout Guidelines
VBAT 5VSUS 5VSUS VBAT
R1 1M 0402
D1 SOD323 C1 0u1 R2 10R 0402
14
16
U1
15
13
0603 Q1 IRF7811AV DH LX 12 11 R4 7k87 ILIM VDDP 10 0402 C6 Q2 FDS6676S + 220u/25m 7343 + 220u/25m 7343 C7 9 L1 2u2 VOUT C2 2n2/50V 0402 C3 0u1/25V 0603 C4 10u/25V 1210
TON
EN/PSV
VOUT C5 56p 0402 R3 20k0 0402
1 2 3 4
VOUT VCCA
SC411
FB PGD
PGOOD R5 14k3 0402
VSSA
TPAD
C8 1nF 0402
C9
PGND 7
NC
5
6
8
1uF 0603
DL
BST
NC
VBAT = 8V to 20V VOUT = 1.2V @ 6A
C10 1uF 0603
Figure 4: Reference Design One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and maximize heat dissipation. The IC ground reference, VSSA, and the power ground pin, PGND, should both connect directly to the device thermal pad. The thermal pad should connect to the ground plane(s) using multiple vias. The VOUT feedback trace must be kept far away from noise sources such as switching nodes, inductors and gate drives. Route the feedback trace in a quiet layer (if possible) from the output capacitor back to the chip. All components should be located adjacent to their respective pins with an emphasis on the chip decoupling capacitors (VCCA and VDDP) and the components that are shown connecting to VSSA in the above schematic. Make any ground connections simply to the ground plane. Power sections should connect directly to the ground plane(s) using multiple vias as required for current handling (including the chip power ground connections). Power components should be placed to minimize loops and reduce losses. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not use "minimum" land patterns for power components. Minimize trace lengths between the gate drivers and the gates of the MOSFETs to reduce parasitic impedances (and MOSFET switching losses), the low-side MOSFET is most critical. Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling requirements (and to reduce parasitics) if routed on more than one layer. Current sense connections must always be made using Kelvin connections to ensure an accurate signal, with the current limit resistor located at the device. We will examine the reference design used in the Design Procedure section while explaining the layout guidelines in more detail.
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SC411
POWER MANAGEMENT
The layout can be considered in two parts, the control section referenced to VSSA and the power section. Looking at the control section first, locate all components referenced to VSSA on the schematic and place these components at the chip. Drop vias to the ground plane as needed.
VBAT 5VSUS 5VSUS
R1 1M 0402
R2 10R 0402
15
16
U1
14
EN/PSV
TON
VOUT C5 56p 0402 R3 20k0 0402
BST
NC
13
1 2 3 4
VOUT VCCA
DH LX
12 11 10 9
SC411
FB PGD ILIM VDDP
C8 1nF 0402
C9
TPAD
PGND 7
VSSA
NC
5
6
8
1uF 0603
DL
R5 14k3 0402
C10 1uF 0603
Figure 5: Components Connected to VSSA
Figure 6: Control Section Example In Figure 6 above, all components referenced to VSSA have been placed and connected to the ground plane with vias. Decoupling capacitors C9 and C10 are as close as possible to their pins and connected to the ground plane with vias. Note how the VSSA and PGND pins are connected directly to the thermal pad, which has 4 vias to the ground plane (not shown).
(c) 2007 Semtech Corp. 18 www.semtech.com
SC411
POWER MANAGEMENT
As shown below, VOUT should be routed away from noisy traces (such as BST, DH, DL and LX) and in a quiet layer (if possible) to the output capacitor(s).
16
U1
15
14 NC
VOUT C5 56p 0402 R3 20k0 0402
EN/PSV
TON
BST
13
1 2 3 4
VOUT VCCA
DH LX
12 11 10 9 C6 + + 220u/25m 220u/25m 7343 7343 C7
SC411
FB PGD
PGND
ILIM VDDP
VOUT
VSSA
TPAD
NC
5
6
7
Figure 7: VOUT Sense Trace Routing Next, the schematic in Figure 8 below shows the power section. The highest di/dts occur in the input loop (highlighted in red) and thus this loop should be kept as small as possible.
VBAT
Q1 IR F 7811AV
8
DL
R5 14k3 0402
C2 2n2/50V 0402 L1 2u2
C3 0u1/25V 0603
C4 10u/25V 1210
VOU T C6 Q2 F D S6676S + 220u/25m 7343 + 220u/25m 7343 C7
Figure 8: Power Section and Input Loop The input capacitors should be placed with the highest frequency capacitors closest to the loop to reduce EMI. Use large copper pours to minimize losses and parasitics. See Figure 9 for an example.
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SC411
POWER MANAGEMENT
Figure 9: Power Component Placement and Copper Pours Key points for the power section: 1) There should be a very small input loop, well decoupled. 2) The phase node should be a large copper pour, but compact since this is the noisiest node. 3) Input power ground and output power ground should not connect directly, but through the ground planes instead. 4) The current limit resistor should be placed as close as possible to the ILIM and LX pins. Connecting the control and power sections should be accomplished as follows (see Figure 10 on the following page): 1) Route VOUT in a "quiet" layer away from noise sources. 2) Route DL, DH and LX (low side FET gate drive, high side FET gate drive and phase node) to chip using wide traces with multiple vias if using more than one layer. These connections to be as short as possible for loop minimization, with a length to width ratio less than 20:1 to minimize impedance. DL is the most critical gate drive, with power ground as its return path. LX is the noisiest node in the circuit, switching between VBAT and ground at high frequencies, thus should be kept as short as practical. DH has LX as its return path. 3) BST is also a noisy node and should be kept as short as possible. 4) Connect PGND and VSSA directly to the thermal pad, and connect the thermal pad to the ground plane using multiple vias.
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SC411
POWER MANAGEMENT
16
U1
13
15
14
EN/PSV
TON
Q1 IRF7811AV DH LX 12 11 R4 7k87 ILIM VDDP 10 9 0402 Q2 FDS6676S L1 2u2
1 2 3 4
VOUT VCCA
SC411
FB PGD
VSSA
NC
TPAD
PGND 7
5
6
Figure 10: Connecting the Control and Power Sections Phase nodes (black) to be copper islands (preferred) or wide copper traces. Gate drive traces (red) and phase node traces (blue) to be wide copper traces (L:W < 20:1) and as short as possible, with DL the most critical.
VBAT
5VSUS
8
DL
BST
NC
5VSUS
VBAT
R1 806k 0402
D1 SOD323 R2 10R 0402
U1
TON
EN/PSV
NC
BST
C1 0u1 0603 12 11 R4 7k15 ILIM VDDP 10 0402 9
15
16
14
13
Q1 IRF7821
C2 2n2/50V 0402
C3 0u1/25V 0603
C4 10u/25V 1210
VOUT C5 220p 0402 R3 28k 0402
1 2 3
VOUT VCCA FB PGD
DH LX
SC411
VOUT L1 1u5 + C6 470u/15m 7343 + C7 470u/15m 7343
PGOOD R5 20k 0402
4
Q2 IRF7832
VSSA
TPAD
C8 1nF 0402
C9 NC 1uF 0603
PGND 7
5
6
8
DL
VBAT = 8V to 20V VOUT = 1.2V @ 10A
C10 1uF 0603
L1 = 1.5uH Vishay IHLP 5050CE C6, C7 = 470uF / 15milli ohm Sanyo POS Cap 2R5TPE470MF
Figure 11: High Efficiency Design
(c) 2007 Semtech Corp. 21 www.semtech.com
SC411
POWER MANAGEMENT Typical Characteristics
For efficiency charts, refer to High Efficiency Design, Figure 11 on page 21. For all other data, refer to the Reference Design, Figure 4 on Page 17.
1.2V Efficiency (Power Save Mode) (High Efficiency Design, Page 21)
100 95 90 85 Efficiency (%) 80 75 70 65 60 55 50 0 1 2 3 4 IOUT (A) 5 6 7 8 9 10
VBAT = 8V
1.2V Efficiency (Continuous Conduction Mode) (High Efficiency Design, Page 21)
100 95 90 85 Efficiency (%) 80 75 70 65 60 55 50 0 1 2 3 4 5 6 IOUT (A) 7 8 9 10
VBAT = 20V VBAT = 8V
VBAT = 20V
1.2V Output Voltage (Power Save Mode) vs. Output Current vs. Input Voltage
1.220 1.216 1.212 1.208 VBAT = 20V
1.2V Output Voltage (Continuous Conduction Mode) vs. Output Current vs. Input Voltage
1.220 1.216 1.212 1.208 VBAT = 20V
VOUT (V)
1.200 1.196 1.192 1.188 1.184 1.180 0 1 2 3 IOUT (A) 4 5 6 VBAT = 8V
VOUT (V)
1.204
1.204 1.200 1.196 1.192 1.188 1.184 1.180 0 1 2
VBAT = 8V
3 IOUT (A)
4
5
6
1.2V Switching Frequency (Power Save Mode) vs. Output Current vs. Input Voltage
400 VBAT = 8V 350 300
1.2V Switching Frequency (Continuous Conduction Mode) vs. Output Current vs. Input Voltage
400 VBAT = 8V 350 300
Frequency (kHz)
250 VBAT = 20V 200 150 100 50 0 0 1 2 3 IOUT (A) 4 5 6
Frequency (kHz)
250 VBAT = 20V 200 150 100 50 0 0 1 2 3 IOUT (A) 4 5 6
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SC411
POWER MANAGEMENT Typical Characteristics
Load Transient Response, Continuous Conduction Mode, 0A to 6A to 0A Trace 1: 1.2V, 50mV/div., AC coupled Trace 2: LX, 20V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 40s/div.
Load Transient Response, Continuous Conduction Mode, 0A to 6A Zoomed Trace 1: 1.2V, 20mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 10s/div.
Load Transient Response, Continuous Conduction Mode, 6A to 0A Zoomed Trace 1: 1.2V, 50mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 10s/div.
Please refer to Figure 4 on Page 17 for test schematic
(c) 2007 Semtech Corp. 23 www.semtech.com
SC411
POWER MANAGEMENT Typical Characteristics
Load Transient Response, Power Save Mode, 0A to 6A to 0A Trace 1: 1.2V, 50mV/div., AC coupled Trace 2: LX, 20V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 40s/div.
Startup (CCM), EN/PSV 0V to Floating Trace 1: 1.2V, 20mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 10s/div.
Load Transient Response, Power Save Mode, 6A to 0A Zoomed Trace 1: 1.2V, 50mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 10s/div.
Please refer to Figure 4 on Page 17 for test schematic
(c) 2007 Semtech Corp. 24 www.semtech.com
SC411
POWER MANAGEMENT Typical Characteristics
Startup (PSV), EN/PSV Going High Trace 1: 1.2V, 0.5V/div. Trace 2: LX, 10V/div Trace 3: EN/PSV, 5V/div Trace 4: PGD, 5V/div. Timebase: 1ms/div.
Startup (CCM), EN/PSV 0V to Floating Trace 1: 1.2V, 0.5V/div. Trace 2: LX, 10V/div Trace 3: EN/PSV, 5V/div Trace 4: PGD, 5V/div. Timebase: 1ms/div.
Please refer to Figure 4 on Page 17 for test schematic
(c) 2007 Semtech Corp. 25 www.semtech.com
SC411
POWER MANAGEMENT Outline Drawing - MLPQ-16
DIMENSIONS MILLIMETERS INCHES MIN NOM MAX MIN NOM MAX
.031 .040 .000 .002 (.008) .010 .012 .014 .153 .157 .161 .079 .085 .089 .153 .157 .161 .079 .085 .089 .026 BSC .012 .016 .020 16 .003 .004 0.80 1.00 0.00 0.05 (0.20) 0.25 0.30 0.35 3.90 4.00 4.10 2.00 2.15 2.25 3.90 4.00 4.10 2.00 2.15 2.25 0.65 BSC 0.30 0.40 0.50 16 0.08 0.10
DIM
A D B
A A1 A2 b D D1 E E1 e L N aaa bbb
PIN 1 INDICATOR (LASER MARK)
E
A2 A aaa C A1 D1 e/2 LxN
E/2
C
SEATING PLANE
E1
2 1 N e D/2 bxN bbb CAB
NOTES: 1. 2. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
Marking Information
Top Marking
SC411 yyww xxxxx xxxxx
yyww = Date Code (Example: 0552) xxxxx = Semtech Lot Number (Example: E9010) xxxxx = (Example: 1-100)
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SC411
POWER MANAGEMENT Land Pattern - MLPQ-16
K
DIM
2x (C) H 2x G 2x Z C G H K P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.152) .114 .091 .091 .026 .016 .037 .189 (3.85) 2.90 2.30 2.30 0.65 0.40 0.95 4.80
Y X P
NOTES: 1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804
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